ACM-SIGDA
Design Automation Technology and Design Manufacturing Interface for Deep Submicron Integrated Circuits
Interconnect Analysis
Based on Session 4D of ICCAD-2000
Hierarchical Interconnect Circuit Models
Author: Michael W. Beattie - Carnegie Mellon Univ., Pittsburgh, PA
Abstract: The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable proportions. Interconnect extraction tools employ hierarchy to manage complexity, but this hierarchy is discarded via eliminating far away coupling terms when the equivalent RLC circuits are formed. The increasing dominance of capacitance coupling along with the emergence of on-chip inductance, however, makes the composite effect of far-away couplings increasingly evident. Even if newly enforced design rules and practices will ultimately obviate the need for modeling these couplings for design verification, some approximation of the "exact" solution is required to validate these rules. This paper proposes an efficient hierarchical equivalent circuit representation of interconnect parasitics that utilizes the efficient hierarchical long distance modeling already existing within extractors. Results from a prototype simulator based on these hierarchical models demonstrates the simulation inaccuracy incurred when the far-away coupling terms are ignored. Such a form of interconnect modeling may provide the key to hierarchical modeling of electromagnetic interactions between large components on future gigascale systems.
Hurwitz Stable Reduced Order Modeling for RLC Interconnect Tree
Author: Xiaodong Yang, Univ. of California at San Diego, La Jolla, CA
Abstract: We present a new realizable reduced order modeling technique for RLC interconnect trees. Both lumped and distributed wire models can be used with this technique. Provable stability is achieved by using Hurwitz polynomials. Moment computation process is avoided but moments can still be matched implicitly. In experiments, the proposed Hurwitz three-pole model can accurately and efficiently capture inductive effect for both near end and far end nodes.
An "Effective" Capacitance Based Delay Metric for RC Interconnect
Author: Chandramouli V. Kashyap - IBM Corporation, Austin, TX
Abstract: Efficient, yet accurate delay estimation for RC interconnect is required for the optimization loop of timing-driven physical design tools. For many applications, the Elmore delay metric [4] has been widely used due to its efficiency and ease of use. However, it is well known that the Elmore metric can have significant error since it ignores the resistive shielding of down-stream capacitance. We present a new interconnect metric called ECM that accounts for this resistive shielding by computing an effective capacitance to model the downstream capacitance. ECM can also be computed with the same complexity as the Elmore delay and does not require the computation of moments. Experiments show that ECM is significantly more accurate than Elmore delay and is competitive with other metrics that use multiple moments.