Past Projects (1999-2004)

Apollo Testbed

We research three major areas in low power design of VLSI circuits and systems: software and system level power prediction and optimization, architectural/behavioral power estimation and optimization, and system-level dynamic power management.

We investigate the problem of simultaneous scheduling and mapping of the computational and communication processes in a generalized task flow graph to HW/SW resources on a VLSI chip so as to minimize the energy dissipation while satisfying a given deadline and/or throughput constraint. As part of this research we examine the problem of modeling energy-latency characteristics of a given application program (for example, specified in a standard programming language such as C/C++) which is to be mapped to custom hardware and/or run on an embedded processor. We develop efficient, yet accurate, estimators at this high-level of design abstraction without having to do detailed compilation of the application program into the hardware and/or software components. This capability is in turn essential in achieving effective power-aware hardware/software co-design. At the same time we develop optimization techniques for power-conscious compiler targeting the StrongARM microprocessor. We research a number of problems related to power analysis and optimization at the behavioral/architectural level. In particular, we address early power estimation for combinational and sequential logic blocks. Examples include power estimation of a finite state machine circuit prior to state encoding, or of a combinational logic circuit before logic synthesis and mapping. We also develop power characterization of Intellectual Property (IP) cores at the architectural level and develop an automatic clock-gating tool for HDL descriptions. We consider dynamic power management techniques, which exploit the idleness of system components, and study the problem of determining optimal management policies for a variety of system models. In particular, we focus on operating system (OS) directed control policies and seek to develop realistic models of the hardware and software components and the system environment.

The key research results include development of prototype software programs that perform power prediction of C/C++ and HDL descriptions of complex applications and systems, provide system-level component modeling and characterization for power, and optimize the application software (C/C++ or HDL) and the system software (OS) to achieve low power dissipation.

Analysis and Design Techniques for Battery-Powered Digital CMOS Circuits

In the past, the major concerns of the VLSI designer were area, speed, and cost; power consideration was typically of secondary importance. In recent years, however, this has begun to change and, increasingly, power is being given comparable weight to other design considerations. Several factors have contributed to this trend, including the remarkable success and growth of the class of battery-powered, personal computing devices and wireless communications systems that demand high-speed computation and complex functionality with low power consumption. In these applications, extending the battery service life is a critical design concern. There also exists a significant pressure for producers of high-end products to reduce their power consumption. The main driving factors for lower power dissipation in these products are the cost associated with packaging and cooling as well as the circuit reliability.

Our research focuses on the problem of maximizing the battery service life in battery-powered CMOS circuits. In particular, we recently proposed an integrated model of the VLSI hardware and the battery sub-system that powers it. We showed that, under this model and for a fixed operating voltage, the battery efficiency (or utilization factor) decreases as the average discharge current from the battery increases. The implication is that the battery life is a super-linear function of the average discharge current. Furthermore, even if the average discharge current remains the same, different discharge current profiles (distributions) may result in very different battery lifetimes. The maximum battery life is achieved when the variance of the discharge current distribution is minimized. Finally, we demonstrated that accounting for the dependence of battery capacity on the average discharge current changes the shape of the energy-delay trade-off curve and hence the value of the operating voltage that results in the optimum energy-delay product for the target circuit. Consequently, we proposed a more accurate metric (i.e., the battery discharge rate times delay product as opposed to the energy-delay product) for comparing various low power optimization methodologies and techniques targeted toward battery-powered electronics. Analytical derivations as well as simulation results demonstrate the importance of correct modeling of the battery-hardware system as a whole.

Our research has far-reaching implications for the design of battery-powered electronics by shifting the focus from power and energy minimization to battery service life maximization. It also brings up a number of new and exciting research problems, including, but not limited to, static and dynamic voltage scaling rules to maximize the battery service life subject to performance constraints, optimal choice of battery cells for a given VLSI circuit, circuit and architectural design of the VLSI system hardware to match the output characteristics of the battery cells that power it, use of multiple battery cells and dynamic power management schemes to maximize the service life of the battery subsystem, and even integrated on-chip battery-hardware design (micro-batteries for micro-electronics).

Portable electronic devices tend to be much more complex than a single VLSI chip; They contain many components, ranging from digital and analog to electro-mechanical and electro-chemical. Hence reducing power consumption only in the digital VLSI circuits is insufficient. System designers have started to respond to the requirement of power-constrained system designs by a combination of technological advances and architectural improvements. Dynamic power management which refers to selective shut-off or slow-down of system components that are idle or underutilized has proven to be a particularly effective technique. Incorporating an effectual dynamic power management scheme in the design of an already-complex system is a difficult process that may require many design iterations and careful debugging and validation. The goal of a dynamic power management policy is to reduce the power consumption of an electronic system by putting system components into different states, each representing certain performance and power consumption level. The policy determines the type and timing of theses transitions based on the system history, workload and performance constraints.

Our research focuses on the development of an abstract stochastic model of a power-managed electronic system and formulating the problem of system-level power management as a stochastic optimization problem based on the theories of continuous-time Markov decision processes and stochastic networks. This problem will be solved exactly and efficiently using a "policy iteration" approach. Extensions to more complex systems, non-stationary system behavior and non-Markovian decision making will be considered.

Design Methodologies and Techniques for Temperature-dependent Reliability, Performance and Signal Integrity Analysis and Optimization of VLSI Interconnects

Due to the ever-increasing failure rates in DSM interconnects, interconnect reliability has become a critical design concern in today's VLSI circuits. However, interconnect reliability and performance (i.e., speed) are tightly coupled and any approach to improve one metric has to consider its effect on the other. Temperature plays a very important role in determining both circuit reliability and performance. The proposed research focuses on detailed yet efficient characterization and quantification of electromigration (EM) and thermomigration (TM) induced failures in VLSI interconnect as well as design automation techniques to combat and control these failures. These techniques will work in a two-dimensional tradeoff space of performance and reliability (PR-space). The proposed research is expected to advance our understanding of EM and especially TM-induced failures in integrated circuits (IC's) and, at the same time, produce guidelines, algorithms, and tools for achieving a non-dominated operating point in the PR-space.

Our work also focuses on the analysis and modeling of non-uniform chip temperature profile and the study of its effects on different aspects of signal integrity in very high performance VLSI interconnects. First, we will develop computationally efficient methods to calculate the thermal profile of VLSI interconnect lines. A temperature-dependent distributed RC interconnect delay model will be developed next. The model can be applied to a wide variety of interconnect layouts and temperature distributions to quantify the impact of these thermal non-uniformities on signal integrity issues. Using this model, we will show that global nets (including clock and power/ground distribution networks as well as long busses and set/reset lines) are the nets that are the most vulnerable to the thermal non-uniformities in the substrate. We will therefore develop computer-aided design techniques for constructing a thermally-driven zero skew clock routing tree, a power/ground distribution network, optimal buffer insertion in long interconnect lines, and, more generally, chip-level dynamic thermal management policies.

Power-Aware Memory Bus Encoding

This research develops encoding techniques to minimize the switching activity on a time-multiplexed Dynamic RAM (DRAM) address bus. The DRAM switching activity can be classified either as external (between two consecutive addresses) or internal (between the row and column addresses of the same address). For external switching activity in a sequential access pattern, we will develop an optimal encoding, PYRAMID code. Extensions of the basic code address different types of DRAM devices and bus architectures, and explore static vs. dynamic coding schemes. To minimize internal switching activity, we propose scattered paging and redundant coding techniques for both random and sequential access patterns. The proposed codes are expected to reduce power dissipation on the memory bus by a factor of two or more.

We also develop encoding techniques for minimizing the switched capacitance on a non-multiplexed address bus between the processor and static memory. More precisely, we have developed the ALBOZ code, which is constructed based on transition signaling and the limited-weight codes, and with enhancements to make it adaptive and irredundant, results in up to 87% reduction in the bus switching activity at the expense of a small area overhead for realizing the encoder/decoder circuitry. Furthermore, building on T0 and Offset-Xor encoding techniques, we have developed three irredundant bus-encoding techniques that decrease switching activity on the memory address bus by up to 83% without the need for redundant bus lines. The power dissipation of encoder and decoder circuitry has also been calculated and shown to be small in comparison with the power savings on the memory address bus itself.

Apollo: Adaptive Power Optimization and Control for the Land Warrior

Project URL: Apollo Testbed

The Apollo project aims at significantly reducing power dissipation of next-generation mobile DoD computing and communication systems by means of operating system-directed power management, power-aware software compilation, and system-level synthesis and optimization of the integrated hardware/software platform subject to performance and quality-of-service constraints.

We consider dynamic power management techniques and study the problem of determining optimal management policies for a variety of system models. In particular, we focus on operating system (OS) directed control policies and seek to develop realistic models of the hardware and software components and the system environment in the Land Warrior System (LWS). We characterize power consumption of common arithmetic logic and memory blocks and develop instruction-level power macro-models for the StrongARM microprocessor and TI's digital signal processor 320c-5410 in addition to the major subsystems in the (next-generation) LWS.

We investigate the problem of developing techniques for power-conscious architectural organization and optimization techniques targeting a StrongARM-based hardware platform that we are constructing based on the Intel's Assabet and Neponset boards plus a number of external devices. This platform is called the Apollo Testbed (AT). We also develop system and application software for the AT. This task will include development of the ARMLinux drivers for all external devices, the "map" application, and the utility software needed for the AT usage scenario that is provided to us by the IPM team of the Army CECOM.

We develop encoding techniques to minimize the switching activity on a time-multiplexed Dynamic RAM (DRAM) address bus. We develop redundant (i.e., with INVERT bit) memory bus encoding techniques that reduce the switching activity on the bus between the FLASH memory and the processor. The proposed codes are expected to reduce power dissipation on the memory bus by a factor of two or more. We develop algorithms and techniques for power optimization of the FLASH and main memory hierarchy in the AT. More precisely, we explore use of different data representations for the images stored in the map database so as to reduce power-consuming accesses to the FLASH memory (which acts as the secondary storage in the AT) at the expense of more intensive computations on the SA 1110. We study and analyze the impact of various architectural optimization techniques on the power saving of the AT. Such techniques include power optimization and control for the LCD, the camcorder, and the network (wireless LAN) interface card.

This work is done in collaboration with Prof. Niraj Jha of Princeton University. Dr. Jha will tackle both periodic and aperiodic task graphs, automatically generate and transform task graphs from the system specification, estimate system power and synthesize low-power system architectures. The system synthesis tools that will be developed include all supporting databases and simulation engines. The tools will synthesize a given system specification written in C or Hardware Description Language (HDL) into a low-power system architecture. He will analyze, model and optimize the power consumed by a real-time operating system (RTOS). He will develop behavioral synthesis tools for low power application-specific integrated circuits (ASICs). The work will be implemented on top of the Princeton university's synthesis system called IMPACT. Additional research topics are common-case computation, leakage power optimization and run-time adaptation in behavioral synthesis for low power.

Low-Power Fanout Optimization

Low-Power Fanout Optimization Using MTCMOS and Multi-Vt Techniques

Although much research has been done to address fanout optimization problem in VLSI circuits, there is little work on low-power fanout optimization. More specifically, since both capacitive and leakage power dissipation of a fanout chain are proportional to its area, it has been widely accepted that power minimization of the fanout tree is equivalent to its area optimization. We have shown that due to short-circuit power dissipation, minimizing area does not necessarily result in a minimized power dissipation solution. In particular, the solution obtained from an area optimized fanout tree may dissipate excessive short-circuit power. We formulate the problem of minimizing the power dissipation of a fanout chain and show how to build a fanout tree out of these power-optimized chains. Additionally, to suppress the leakage power dissipation in a fanout tree, we use multi channel length (LGate) and multi-Vt techniques. In the presence of multi-LGate and multi-Vt options, we accurately model the delay and power dissipation of inverters as posynomials; therefore, our proposed problem formulation results in a convex mathematical program comprising of a posynomial objective function with posynomial inequality constraints which can be efficiently solved.