High-level (behavioral) synthesis is the process for synthesizing the circuit structure in RTL (register transfer level) from the input behavioral descriptions (or algorithms) written in hardware description language such as VHDL or HardwareC. The high-level of abstraction provide more powerful and complete ways to explore the design space within much shorter turn around time than the tasks done by human designers. For an analogy, it is like in the software domain to produce the assembly codes from high level language like C or pascal by using the compiler. Previously, programmer have to write assembly codes and translate to machine code by hand or by assembler. The design automation process in hardware world is also moing to higer level.
Normally the input to a high-level synthesis process is some HDL, such as VHDL. It is then pass to some front end tools like VHDL parser and translator to obtain some intermediate format. Most systems use something like control flow graph and/or data flow graph or the combination of the two like CDFG as the intermediate format. The behaviorial transformation is an optimization process which works on the CDFG to provide better equivalent CDFG to be used in the coming phases. The new CDFG will be used in scheduling, allocation and binding processes. There is no fixed order for the above three process. However, most high-level synthesis follow the order: scheduling then allocation and binding.
The behavioral synthesis process consists of three phases: allocation, assignment and scheduling. These processes determine how many instances of each resource are needed (allocation), on what resource a computational operation will be performed (assignment or binding) and when it will be executed (scheduling). Traditionally, behavioral synthesis attempts to minimize the number of resources to perform a task in a given time or tries to minimize the execution time for a given set of resources.